次世代DRAM技術 Hybrid Memory Cube (HMC) の製品化を目指すHMCコンソーシアムが、最初の仕様書 HMC Specification v1.0 を公開しました。

HMCはメモリチップの三次元積層とシリコン貫通電極 (TSV, Through-Sillicon Via)、メモリコントローラの統合など新技術・新アーキテクチャを採用することで、現行のDDR3と比較して大幅な高速化と低消費電力、実装面積の削減を可能にする新しいDRAM規格の名称。
HMCは Micron やサムスンが中心となって提唱した規格で、コンソーシアムには Developer Members として上記2社のほかSK hynix や ARM、HP、Alteraなど9社が、Adopter Member と合わせて100以上の企業や研究機関が名を連ねています。

HMCは次世代を名乗るだけあって物理層も論理層も新しく、現行の DDR3 DRAMなどとは互換性がありません。物理的には、メモリコントローラと外部のCPUやGPUとのシリアル通信インターフェースを兼ねるロジック層の上に、TSVで貫通接続されたメモリチップを積層した構造。

TSV構造で広帯域と低消費電力を実現し、またメモリモジュール側にコントローラを内蔵してマルチレーンのシリアル通信をすることで、マルチコアプロセッサやGPUが要求する並列アクセスに応えるとされています。

具体的な数字は、インターフェース速度はDDR3比で15倍以上、消費電力/ビットは70%減、実装面積はRDIMM比で90%近く減など。複数リンクをまとめたモジュールとしての最大通信速度は双方向に160GB/秒。

(1レーンあたり、双方向に10, 12.5 または 15Gbps (Short Reachの場合)。16レーンまたは半分の8レーンで1シリアルリンク。初版規格では1キューブあたり4リンクや8リンク。 なので、10Gbpsの16レーンで双方向 20GBps (40GBps)。40GBps x 8リンクのモジュールなら320GBps。レーンあたりの転送速度は、v1.0以降の規格では28Gbps (SR)まで高速化を目指す。)

DDR4が現行の規格と互換性を保ったまま漸進的な高速化を図るのに対して、HMCはアーキテクチャから変革することで、プロセッサの高速化に追いつけない「メモリの壁」を破る革新的規格という位置づけです。

今回正式仕様として承認された 1.0 spec は、プロセッサとの距離 8 - 10インチ(一般的なPCマザーボード程度)に対応するSR (Short Reach)と、よりプロセッサに近い距離で実装する用途向けの USR (Ultra Short Reach)を定めています。HMC コンソーシアムによると、SR規格のハイブリッドメモリーキューブは今年後半、USR規格のHMCは来年にも登場する予定。



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Hybrid Memory Cube Consortium Heralds 2013 as Turning Point for High-Performance Memory ICs, Gains Rapid Consensus for Final Specification and Decision to Renew Consortium

Collaboration Among 100 Developers and Adopters Will Enable New Disruptive Computing Solutions for Wide Range of Industrial to Consumer Segments


BOISE, Idaho and SEOUL, Korea (April 2, 2013) - More than 100 developer and adopter members of the Hybrid Memory Cube Consortium (HMCC) today announced they've reached consensus for the global standard that will deliver a much-anticipated, disruptive memory computing solution. Developed in only 17 months, the final specification marks the turning point for designers in a wide range of segments-from networking and high-performance computing, to industrial and beyond-to begin designing Hybrid Memory Cube (HMC) technology into future products.

A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine highperformance logic with state-of-the-art DRAM. With this first HMC milestone reached so quickly, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards.

"The consensus we have among major memory companies and many others in the industry will contribute significantly to the launch of this promising technology." said Jim Elliott, Vice President, Memory Planning and Product Marketing, Samsung Semiconductor, Inc. "As a result of the work of the HMCC, IT system designers and manufacturers will be able to get new green memory solutions that outperform other memory options offered today."

"This milestone marks the tearing down of the memory wall," said Robert Feurle, Micron's Vice President for DRAM Marketing. "The industry agreement is going to help drive the fastest possible adoption of HMC technology, resulting in what we believe will be radical improvements to computing systems and, ultimately, consumer applications."

"HMC is a very special offering currently on the radar," said JH Oh, Vice President, DRAM Product Planning and Enabling Group, SK hynix Inc. "HMC brings a new level of capability to memory that provides exponential performance and efficiency gains that will redefine the future of memory."

As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiency. One of the primary challenges facing the industry-and a key motivation for forming the HMCC-is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide. The term "memory wall" has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption.

The HMC standard focuses on alleviating an extremely challenging bandwidth bottleneck while optimizing the performance between processor and memory to drive high-bandwidth memory products scaled for a wide range of applications. The need for more efficient, high-bandwidth memory solutions has become particularly important for servers, high-performance computing, networking, cloud computing and consumer electronics.

The achieved specification provides an advanced, short-reach (SR) and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close-proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement. The next goal for the consortium is to further advance standards designed to increase data rate speeds from 10, 12.5 and 15 gigabits per second (Gb/s) up to 28 Gb/s for SR and from 10 Gb/s up to 15Gb/s for USR. The next-generation specification is projected to gain consortium agreement by the first quarter of 2014.

The HMCC is a focused collaboration of OEMs, enablers and integrators who are cooperating to develop and implement an open interface standard for HMC. More than 100 leading technology companies from Asia, Japan, Europe and the U.S. have joined the effort, including Altera, ARM, Cray, Fujitsu, GLOBALFOUNDRIES, HP, IBM, Marvell, Micron Technology, National Instruments, Open-Silicon, Samsung, SK hynix, ST Microelectronics, Teradyne and Xilinx. Continued collaborations within the consortium could ultimately facilitate new uses in HPC, networking, energy, wireless communications, transportation, security and other semiconductor applications.